.title sch-rnd export using export_spice

*** sch-rnd/export_spice: model card: U1 ***
.MODEL schrnd_U1 d_xor (rise_delay=1.0e-6 fall_delay=2.0e-6
+ input_load=1.0e-12) 

*** sch-rnd/export_spice: model card: bridge_dac_ttl ***
* (C) 2023 Tibor 'Igor2' Palinkas
* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
*
* source: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

.MODEL bridge_dac_ttl dac_bridge(
+ out_low = 0 out_high = 5 out_undef = 1.4
+ input_load = 5.0e-12 t_rise = 50e-9 t_fall = 20e-9)


*** sch-rnd/export_spice: model card: bridge_adc_ttl ***
* (C) 2023 Tibor 'Igor2' Palinkas
* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
*
* source: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

.MODEL bridge_adc_ttl adc_bridge
+      (in_low=0.8 in_high=2.0 rise_delay=1.0e-12 fall_delay=1.0e-12)


*** circuit ***
A_U1 [br_bridge_adc_ttl_0 br_bridge_adc_ttl_1] br_bridge_dac_ttl_0 schrnd_U1
V1 input1 0 PULSE (0 5 1 0.3 0.3 2 10)
V2 input2 0 PULSE (0 5 2 0.3 0.3 2 4)
A_sch_rnd_br_bridge_dac_ttl [br_bridge_dac_ttl_0] [output] bridge_dac_ttl
A_sch_rnd_br_bridge_adc_ttl [input1 input2] [br_bridge_adc_ttl_0 br_bridge_adc_ttl_1] bridge_adc_ttl
R1 output 0 100k

*** sch-rnd/export_spice: commands ***
.control

tran 10ms 6s
plot v(input1)+0.04 v(input2)+0.08 v(output) xlimit 0 6s

.endc
.end
