# 12_bjt_amp_ac: pinout with spice/portmap

## Scope

In this simulation we are going to look at a single-transistor amplifier in frequency domain to verify how it amplifies a sine waves. Compared to the trans variant the only difference is how we specify the transistor pinout and how the simulation setup is configured.

## The schematics

Largely the same as trans variant.

Click the image to get the sch-rnd sheet; also requires this project.lht in the same directory

## Preparing for simulation

### Q1

This example demonstrates using spice/portmap to set the pinout: the stock spice/pinnum attributes has been manually removed from Q1 terminals and a portmap attribute, array type, added to the Q1 symbol. The portmap is:

    {C->spice/pinnum=1}
    {B->spice/pinnum=2}
    {E->spice/pinnum=3}

Since the attribute is called spice/portmap, it does not interfere with the normal portmap attribute (installed by devmap in our example) and it affects the spice workflow only.

The simulation setup process is largely the same as in the base example of dc op point. The simulation setup in this example is called "ac characteristics".

### Modifications

This circuit needs two voltage sources, which are both added as modifications. The first one is a DC 5V source connected to net Vcc (and GND). The second acts as the small signal AC source for the AC analysis, this it has a an AC value (of 0.1 V); it is connected to net in (and GND).

### Sim setup: output config

(Same as in example 06_passive_ac )

This simulation has two output configs, one for displaying the transfer (in decibel) and one for the phase (in radian). The reason for specify them in two separate output is the largely different y scale and unit.

The first output uses ac (dec) for analysis. This will feed in 10 different frequencies per decade and capture the output. This also means the X axis, frequency, is logarithmic (common for frequency domain analysis).

The property to plot is vdb(out), which is the "voltage decibel" of the network called out. Instead of the net name a component-port could be specified within vdb().

The second output uses anlaysis previous, which means no new simulation is ran, but the data of the previous simulation is used. The presentation is also a plot of "out", but using the cph() function, which is the phase in radian.

Simulation setup dialog, third tab, after execution