* (C) 2023 Tibor 'Igor2' Palinkas
* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
*
* source: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

.model bridge_dac_ttl dac_bridge(
+ out_low = 0 out_high = 5 out_undef = 1.4
+ input_load = 5.0e-12 t_rise = 50e-9 t_fall = 20e-9)
